3:50 PM - 4:40 PM
[SC-B-04] Challenges in Si device and process technology for dimensional and voltage scaling
CMOS scaling has been conducted by reducing transistor dimension and supply voltage Vdd. FinFETs having the gate surrounding the channel have been introduced to suppress off-leakage current which becomes unacceptable level for bulk-planar MOSFETs with the gate length of 30 nm and less. With the shrink of the transistor size, random variation caused by discreteness of dopant atoms also causes the characteristics variability significantly. Since the FinFETs can be operated with an undoped channel, the FinFETs can also suppress the characteristics variability effectively. The suppression of the off-leakage, i.e. improvement of the subthreshold slope, and the suppression of the characteristics variability both are beneficial for conducting scaling of Vdd. Half of this lecture is given for the FinFET device and process technology including suppression of the characteristics variability. In order to conduct Vdd scaling further, achievement of steeper on/off characteristics beyond the theoretical limit of MOSFETs will be needed. Latter half of this lecture is given for a silicon-base tunnel FET, which is one of the candidate of the super-steep transistors.