The Japan Society of Applied Physics

4:40 PM - 5:30 PM

[SC-B-05] Future Si functional nano-devices and their important analyzing technologies

Y. Takahashi1 (1.Hokkaido Univ. (Japan))

Higher functionality of Si CMOS logic LSIs has been achieved by means of miniaturization and integration. The progress is in the process of limiting due to the miniaturization difficulties and increase of power density. On the one hand, fabrication technologies for nanoscale structure have been already developed to create new functional devices for quantum computing or neural network for AI (Artificial Intelligence). Here, the fabrication methods and their functionalities are introduced. It is not so hard to make Si single-electron islands though the formation of the tunnel barrier that isolates the island one from the other is still an issue. To build the neural-network hardware for AI, analog nonvolatile memories are needed. There are many candidates, such as ferroelectric memory, resistive memory, phase change memory, etc.
Another important subject for the nanoscale devices is how to analyze the failure mechanism. Here, in-situ observation of the nanoscale devices in a transmission electron microscopy (TEM) is introduced. One of the problems of TEM was that it needs very thin sample less than 100 nm. But now, device size has already less than 100 nm. The method is powerful to analyze the operation mechanisms and reliability of nano-devices.