11:30 AM - 11:45 AM

[B-4-03] A New Architecture of Store Energy and Latency Reduction for Nonvolatile SRAM Based on Spintronics/CMOS-Hybrid Technology

^○D. Kitagata¹, S. Yamamoto¹, S. Sugahara¹ (1.Tokyo Tech (Japan))

https://doi.org/10.7567/SSDM.2018.B-4-03