11:00 〜 13:30

[PS-1-16] Vertical gate-all-around transistors with symmetrical silicided S/D contacts for high performance p-FET devices.

^○G. Larrieu¹, N. Mallet¹, Y. Guerfi¹, F. Cristiano¹, J. Pezard¹, A. Lecestre¹ (1.LAAS CNRS (France))

https://doi.org/10.7567/SSDM.2018.PS-1-16