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[PS-1-21 (Late News)] Circuit speed oriented device design scheme for double gate hetero tunnel FETs

K. Fukuda^1,2, N. Nogami², S. Kunisada²,^○Y. Miyamoto² (1.AIST (Japan), 2.Tokyo Tech (Japan))

https://doi.org/10.7567/SSDM.2019.PS-1-21