Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation

Assawer - Soussou

doi:https://doi.org/10.7567/SSDM.2020.A-5-03

14:45 〜 15:00

[A-5-03] Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation

〇Assawer - Soussou¹, Tom - Schram², Kenichi - Miyaguchi², Ivan - Chakarov³, Bertrand - Parvais², Joseph - Ervin³ (1. COVENTOR(France), 2. IMEC(Belgium), 3. COVENTOR (US)(United States of America))

https://doi.org/10.7567/SSDM.2020.A-5-03

2020 International Conference on Solid State Devices and Materials

[A-5-03] Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation