A Self-Bias NAND Gate and its Application to Non-Overlapping Clock Generator for Extremely Low-Voltage CMOS LSIs

10:00 AM - 10:15 AM

[A-7-02] A Self-Bias NAND Gate and its Application to Non-Overlapping Clock Generator for Extremely Low-Voltage CMOS LSIs

〇Hikaru Sebe¹, Kaori Matsumoto², Ryo Matsuzuka¹, Osamu Maida¹, Daisuke Kanemoto¹, Tetsuya Hirose¹ (1. Osaka Univ.(Japan), 2. Kobe Univ.(Japan))