Understanding the Tunneling Behavior in 2D Based Floating Gate Type Memory Device by Measuring Floating Gate Voltage

Taro Sasaki

doi:https://doi.org/10.7567/SSDM.2020.H-9-04

2:45 PM - 3:00 PM

[H-9-04] Understanding the Tunneling Behavior in 2D Based Floating Gate Type Memory Device by Measuring Floating Gate Voltage

〇Taro Sasaki¹, Keiji Ueno², Takashi Taniguchi³, Kenji Watanabe³, Tomonori Nishimura¹, Kosuke Nagashio¹ (1. Univ. of Tokyo(Japan), 2. Saitama Univ.(Japan), 3. NIMS(Japan))

https://doi.org/10.7567/SSDM.2020.H-9-04

2020 International Conference on Solid State Devices and Materials

[H-9-04] Understanding the Tunneling Behavior in 2D Based Floating Gate Type Memory Device by Measuring Floating Gate Voltage