Experimental Demonstration of High-Gain CMOS Inverter at Low Vdd Down to 0.5 V Consisting of WSe2 n/p FETs

Takamasa Kawanago

doi:https://doi.org/10.7567/SSDM.2021.H-6-05

16:36 〜 16:43

[H-6-05] Experimental Demonstration of High-Gain CMOS Inverter at Low V_dd Down to 0.5 V Consisting of WSe₂ n/p FETs

〇Takamasa Kawanago¹、Takahiro Matsuzaki¹、Ryosuke Kajikawa¹、Iriya Muneta¹、Takuya Hoshii¹、Kuniyuki Kakushima¹、Kazuo Tsutsui¹、Hitoshi Wakabayashi¹ (1.Tokyo Tech.)

https://doi.org/10.7567/SSDM.2021.H-6-05

2021 International Conference on Solid State Devices and Materials

[H-6-05] Experimental Demonstration of High-Gain CMOS Inverter at Low Vdd Down to 0.5 V Consisting of WSe2 n/p FETs

[H-6-05] Experimental Demonstration of High-Gain CMOS Inverter at Low V_dd Down to 0.5 V Consisting of WSe₂ n/p FETs