The Impact of Parasitic RLC and Layout Optimization for Sub-60nm Multi-finger nMOSFETs with Super-350GHz f<sub>MAX</sub> for mm-Wave CMOS

16:43 〜 16:50

[L-2-06] The Impact of Parasitic RLC and Layout Optimization for Sub-60nm Multi-finger nMOSFETs with Super-350GHz f_MAX for mm-Wave CMOS

〇Jyh-Chyurn Guo¹、Jyun-Rong Ou¹、Adhi Cahyo Wijaya¹、Jinq-Min Lin¹ (1.National Yang Ming Chiao-Tung University)