N channel MOSFET were fabricated on intrinsic 60nm-Si SOI substrate using low-temperature sputter-ing SiO2 gate insulator (GI) combined with high pres-sure water annealing (HWA), in order to reveal poten-tial of low-temperature sputtering SiO2 as GI. In order to prevent unwanted contamination of carbon at chan-nel interface from photoresist, resistless process was used. The maximum process temperature after GI formation was 580℃. Resultant characteristics are field effect mobility µ of 676 cm2/Vs, subthreshold swing ss of 122 mV/dec, Vth of 0.9 V, and Ion/Ioff of 6×108.