The Japan Society of Applied Physics

16:00 〜 16:15

[A-2-01] Er 2O 3 top gate MoS 2 FET with EOT lower than 1 nm

Shuhong Li1, Tomonori Nishimura1, Kosuke Nagashio1 (1. Univ. of Tokyo (Japan))

https://doi.org/10.7567/SSDM.2023.A-2-01

Integrating top-gated high dielectric constant material on 2D semiconductor with good scalability possesses high importance while a huge gap includes material selection and integration method prohibits further development. Herein, the thermal evaporation-based deposition of Er2O3 is demonstrated as a promising dielectric material that can be integrated directly on top of MoS2 with superior scalability. An EOT less than 1 nm dual gate MoS2 FET is demonstrated with dielectric physical thickness 3.5-nm and can be operated within 1 V, highlighted as a new alternative applicable for future scaling