11:30 AM - 11:45 AM
[A-6-03] Heterogeneous Integration of 32 × 32 1S1R Crossbar Array using 2D Hafnium Diselenide on Si Platform and its Compute-in-Memory Hardware Featuring Low Latency and High Energy Efficiency
For the first time, we report a heterogeneous 1 kbit (32 × 32) crossbar array (CBA) combining silicon (Si) based selectors and memristors made of two-dimensional (2D) hafnium diselenide (HfSe2). The integration of one-selector-one-memristor (1S1R) via three-dimensional (3D) stacking of 2D HfSe2 achieves low energy (70 pJ) write/read operations and fast speed performance (< 20 ns). Additionally, a low-power sensing circuit is realized to address the power consumption limitation of ADC for the scaling of CBA architecture. The ADC-free circuit comprises a high-accuracy differential subtractor to minimize quantization loss and a time-to-digital converter (TDC)-based converter using FPGA. The hardware successful achieves scalable, multiplexer (MUX)-free parallel compute-in-memory (CIM) and image processing.
