9:15 AM - 9:30 AM
[E-3-02] Novel Stacked Gate All-Around Nanosheet Transistor-Based DRAM
This paper reports a novel stacked DRAM architecture having a Gate all-around (GAA) nanosheet access transistor as potential DRAM for the end of the 2D DRAM roadmap. Using TCAD we investigate the performance and benefits of this architecture and benchmark with conventional saddle fin recessed channel access transistor (SRCAT). We show that compared to SRCAT, nanosheet DRAM shows superior current driving capability, write speed, and storage node leakage. Importantly, nanosheet DRAM shows significantly lower row hammer (RH)-induced failure as compared to SRCAT.