9:30 AM - 9:45 AM
[E-3-03] Exploring Vertical DRAM Architecture using Advanced Pathfinding Techniques
In this article, we demonstrate a pathfinding technique for a new 4F2 Vertical DRAM technology. We are able to identify important process parameters (defined by current process equipment capabilities) that strongly impact yield. We then modify important process parameters in a virtual model to improve yield using process window optimization of the 4F2 Vertical DRAM at specific device target ranges. Using this technique, we initiate pathfinding on a proposed Vertical DRAM device, and predict and improve the yield.