The Japan Society of Applied Physics

2:15 PM - 2:30 PM

[E-7-02] Threshold Voltage Control of LTPS TFTs with MONOS Structure

TETSUYA GOTO1,2, TOMOYUKI SUWA1,2, KEITA KATAYAMA3, SHU NISHIDA3, HIROSHI IKENOUE4, SHIGETOSHI SUGAWA1 (1. Tohoku Univ. (Japan), 2. FAIS (Japan), 3. Kyushu Univ. (Japan), 4. Kochi Tech (Japan))

https://doi.org/10.7567/SSDM.2023.E-7-02

LTPS TFTs with MONOS structure was fabricated to investigate the feasibility of suppressing threshold voltage variations between TFTs. By applying high positive and negative gate bias voltages, threshold voltage could be tuned both positively and negatively by injecting charges to charge trap layer, respectively. Even after tuning, stability of threshold voltage against positive gate bias at the actual circuit operation level was not degraded compared to the case of as-fabricated TFT.