We have successfully developed and fabricated low Ni accumulation symmetric S/D vertical n-channel poly-Si thin-film transistors (LNA-SVTFTs) using dual offset Ni seeding windows and discrete Ni formation technology. The proposed LNA- SVTFTs are S/D symmetric devices and equivalent to dual-gate devices. Therefore, the Ni accumulation induced from dual Ni seeding windows can be centralized in the n+ floating region. The location effects of Ni seeding windows and the channel width effects of poly-Si crystal filtering structure in LNA-SVTFTs are studied. We also develop a novel discrete Ni formation technology to minimize Ni accumulation, which enhances grain size and carrier mobility.