In this work, the impact of back bias (BB) on the random telegraph noise (RTN) in the tensile strained nFETs (t-nFETs) and compressively strained pFET (c-pFETs) co-integrated on 12 inch strained SOI substrate are experimentally investigated. The value and polarity of BB will affect the trap energy level and the extracted interface trap density D_it, leading to the current fluctuation in the RTN spectra. As compared with the t-nFETs, c-pFETs are more sensitive to the change of BB in terms of the trap energy level and current fluctuation. Furthermore, the power spectrum density at different BB conditions are analyzed to study the frequency dependence of noises under different BB. For c-pFETs, RTN is dominant at forward BB while 1/f noise is dominant under reverse BB. Careful design of bias condition is necessary for the noise optimization of the co-integrated CMOS circuits.