Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors

Curtis S Durfee

doi:https://doi.org/10.7567/SSDM.2023.F-7-02

14:00 〜 14:15

[F-7-02] Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors

Curtis S Durfee¹, Ivo Otto², ^○Subhadeep Kal², Shanti Pancharatnam¹, Matthew Flaugh², Toshiki Kanaki², Matthew Rednor², Huimei Zhou¹, Liqiao Qin¹, Juntao Li¹, Luciana Meli¹, Nicolas Loubet¹, Peter Biolsi², Nelson Felix¹ (1. IBM (United States of America), 2. TEL (United States of America))

https://doi.org/10.7567/SSDM.2023.F-7-02

In this paper, we characterize some key strategies to mitigate pFET source/drain (S/D) epi damage during channel release in nanosheet devices without degrading performance by optimizing the inner spacer (IS) length or introducing a buffer prior to SiGe:B S/D deposition. As expected, the DC performance improves with decreased IS length driven by a reduction in R_ext. In addition, we have benchmarked several SiGe etch chemistries with increased process margin to prevent S/D damage and characterize the corresponding device performance.

2023 International Conference on Solid State Devices and Materials

[F-7-02] Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors