4:00 PM - 4:15 PM
[F-8-02] Holistic Analysis of Asymmetry in Vertical Silicon Gate-all-around Nanosheet FETs
Asymmetries characteristics by S/D structures and tapered vertical channels in vertical silicon gate-all-around nanosheet FETs (VFETs) are investigated quantitatively. In nFETs, VFETs having source epi on the top (TopS) drives more on-current (Ion) than those at the bottom (BotS), but RC delay is almost the same. On the other hand, BotS exhibits a much larger Ion and smaller RC delay than TopS in pFETs. Furthermore, Ion increases and RC delay decreases as tapered angles of the vertical channels (Ach) decreases, and BotS generally exhibit smaller RC delay than TopS regardless of Ach in both n/pFETs.