3D Stack Ultra High Resistance Via Matrix by Cu BEOL Structuresin Nano-scaled CMOS Processing Node

Li-Yu Yeh

doi:https://doi.org/10.7567/SSDM.2023.F-8-03

16:15 〜 16:30

[F-8-03] 3D Stack Ultra High Resistance Via Matrix by Cu BEOL Structuresin Nano-scaled CMOS Processing Node

Li-Yu Yeh¹, ^○Ya-Lin Chang¹, Yue-Der Chih², Jonathan Chang², Chrong-Jung Lin¹, Ya-Chin King¹ (1. National Tsing Hua University (Taiwan), 2. Design Technology Platform, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan (Taiwan))

https://doi.org/10.7567/SSDM.2023.F-8-03

This paper introduces a high-resistance structure proposed
in advanced Cu BEOL processes. Inspired by the self-aligned
via process, the via and metal are closely placed to obtain a
high-resistance via (HRV) structure. To alleviate the large
process variation effect, different HRV matrices are proposed
with their performance comparison. The reliability of the
new HRV under voltage and temperature stress has also been
comprehensively evaluated in this study.

2023 International Conference on Solid State Devices and Materials

[F-8-03] 3D Stack Ultra High Resistance Via Matrix by Cu BEOL Structuresin Nano-scaled CMOS Processing Node