The Japan Society of Applied Physics

2:45 PM - 3:00 PM

[G-1-03] Metal Pitch 18nm Semi-Damascene Spacer-is-Dielectric SADP Process Integration for Beyond A10 Technology Node

Chen Wu1, Vincent Renaud1, Stephane Lariviere1, Stefan Decoster1, Yannick Hermans1, Quoc Toan Le1, Hanne DeCoster1, Bart Kenens1, Diana Tsvetanova1, Alfonso Sepulveda Marquez1, Gayle Murdoch1, Seongho Park1, Zsolt Tokei1 (1. imec (Belgium))

https://doi.org/10.7567/SSDM.2023.G-1-03

In metal pitch (MP) of 18nm Semi-Damascene SADP process integrations, Spacer-is-Dielectric is favored due to its capability of fabricating core and gap defined metal lines with variable CDs. In the proposed flow, the queue-time between TiN spacer deposition and etch causes TiN surface oxidation inducing process variation in TiN etch bias. By performing extra O3 rinsing or TiO2 deposition, the etch bias can be stabilized to the process target. In the factorial study of aSi core CD after trim and TiN spacer thickness, the process window is derived resulting in MP18nm core, gap and space patterned properly post spacer pull with equal CDs around 9nm.