The Japan Society of Applied Physics

09:45 〜 10:00

[J-3-04] Low Quiescent Current LDO with FVF-Based PSRR Enhanced Circuit for EEG Recording Wearable Devices

Kenji Mii1, Daisuke Kanemoto1, Tetsuya Hirose1 (1. Osaka Univ. (Japan))

https://doi.org/10.7567/SSDM.2023.J-3-04

This paper proposes a low quiescent current low-dropout regulator (LDO) with a flipped voltage follower (FVF)-based power supply rejection ratio (PSRR)-enhanced circuit for EEG recording devices. The proposed LDO was designed using a 0.18 μm CMOS process. The designed LDO achieved a PSRR that was improved by 18 dB at 15 kHz, compared with the general configuration obtained using measurement results. Quiescent current consumed by the LDO at no-load operation was 648 nA.