The Japan Society of Applied Physics

11:00 AM - 11:15 AM

[K-6-02] Highly Error-tolerant Low Power CiM by Co-design of SLC Mask & MLC Weight Twin FeFETs and Strong Lottery Ticket Hypothesis Neural Network Algorithm

Kenshin Yamauchi1, Ayumu Yamada1, Naoko Misawa1, Seong-Kun Cho1, Kasidit Toprasertpong1, Shinichi Takagi1, Chihiro Matsui1, Ken Takeuchi1 (1. Univ. of Tokyo (Japan))

https://doi.org/10.7567/SSDM.2023.K-6-02

This paper co-designs SLC Mask and MLC Weight Twin FeFET devices and Strong Lottery Ticket Hy-pothesis (SLTH)-based Neural Network (NN) algo-rithm to achieve highly error-tolerant low power Computation-in-Memory (CiM). SLC Mask FeFET masks or not weights stored in MLC Weight FeFET, and CiM power consumption is reduced. SLC Mask FeFET shows 86% inference ac-curacy even at 2,000 endurance cycles. Uniformly randomized VTH weight of MLC Weight FeFET achieves 87% inference accuracy against 10-year da-ta-retention and read-disturb. Moreover, proposed Shared-IL SLTH CiM and Common-mask SLTH CiM save CiM area by sharing select transistor or Mask FeFET.