Supression of Threshold Voltage Instability due to Positive Bias Stress in GaN Planer MOSFETs by Post-Deposition Anneal

Yuki Ichikawa

doi:https://doi.org/10.7567/SSDM.2023.N-1-03

2:45 PM - 3:00 PM

[N-1-03] Supression of Threshold Voltage Instability due to Positive Bias Stress in GaN Planer MOSFETs by Post-Deposition Anneal

^○Yuki Ichikawa¹, Katsunori Ueno², Tsurugi Kondo², Ryo Tanaka², Shinya Takashima², Jun Suda¹ (1. Univ. of Nagoya (Japan), 2. Corp. of Fuji Electric (Japan))

https://doi.org/10.7567/SSDM.2023.N-1-03

Threshold voltage instability due to positive bias stress in GaN planer MOSFETs was investigated. Gate dielec- tric (SiO2) was formed by remote-plasma-assisted chemi- cal vapor deposition on homoepitaxial Mg-doped p-tye GaN. The threshold voltage shift was 5.8 V at a stress volt- age of 30 V for the sample without post-deposition anneal (PDA), while the threshold voltage shift was significantly reduced to 1.4 V for the sample with PDA at 800°C for 30 min. Stress time dependences up to 6000 s were measured, revealing that the main origin of threshold voltage shift is electron trapping into near interfaces traps.

2023 International Conference on Solid State Devices and Materials

[N-1-03] Supression of Threshold Voltage Instability due to Positive Bias Stress in GaN Planer MOSFETs by Post-Deposition Anneal