A new wafer warpage model is proposed for a full process design of trench field-plate power MOSFETs using large size wafer. A stress balance between front and back sides of wafers has become increasingly serious to design full process integration, because lateral pitch narrowing of deep trenches with thick oxide are employed for on-resistance reduction. Two methods were compared to estimate 200 mmf Si-wafer warpage after trench etching and oxidation process. The mechanical stress generated by the oxidation process in several cell units was calculated using a 3D-simulation. As the first approach, the wafer warpage was converted from the displacement of the cell units directly. In the second approach, the wafer warpage was estimated by the surface film stress, which was calculated in the 3D-simulation. The second approach showed good agreement with experimental results and would be applicable to 300 mmf Si process and other Si power device process designs.