[PS-1-02] A Simple Way to Fabricate Si N-/P-Channels CFET Using Si/Ge Multilayer Epitaxy, Direct S/D Implantation and Ge Selective Etching
In this work, a simple way was proposed for fabricating CFET devices. The starting material is a structure of Si/Ge/Si epitaxial multilayers. The source/drains (S/Ds) for the both devices were formed in advance by direct B and P implan-tations respectively. Isolation of top n-channel and bottom p-channel was achieved by etching away the middle Ge sacrificial layer using H2O2 solution. Because the etching selectivity is almost near infinity, the structure of n-Si channel stacking over p-Si channel is perfect. Finally, the functional bottom Si pFET and top Si nFET are demon-strated.