The Japan Society of Applied Physics

[PS-1-14] Nano CMOS Devices Layout Optimization for Super-350GHz fMAX in mmWave and Sub-THz CMOS Applications

Adhi Cahyo Wijaya1, Jinq Min Lin1, Jyh Chyurn Guo1 (1. National Yang Ming Chiao Tung University (Taiwan))

https://doi.org/10.7567/SSDM.2023.PS-1-14

New device layouts and optimization for an effective boost of high frequency performance aimed at super-350 GHz fMAX are first proposed and realized in TSMC 40-nm CMOS technology. Our invented new device layouts, namely multi-finger (MF) MOSFETs in multi-array (MA) can reach a simultaneous reduction of parasitic resistances and inductances at all of the 4 terminals (4T) such as gate/drain/source/body (G/D/S/B) in 4T MF MOSFETs which are required to realize various circuit topologies like common gate (CG), common drain (CD), and common source (CS) in RF/mm-Wave circuits design. The optimized MF layout in MA can reach the maximum fMAX up to 384-GHz/376-GHz for 3T/4T MF nMOSFETs that is 24%/25.6% enhancement versus the conventional MF nMOSFET in single-array (SA). This record high fMAX achieved in 40nm CMOS technology makes it a premium platform for mm-Wave/Sub-THz circuits design.