[PS-2-09] Design Space Exploration of Dual-Port FeFET for Low-Voltage Applications
We have comprehensively explored the design space of dual-port ferroelectric FET (FeFET) with ultrathin body and buried-oxide (UTBB) structure for low-voltage operation considering the requirements in memory window (MW) and the interfacial layer (IL) reliability. Our investigation shows that, with an adequate design in the BOX thickness to balance the MW amplification and the required read voltage, the design space of the dual-port FeFET can substantially expand toward the low writing-voltage and low ferroelectric-thickness region. Our study also indicates that combining the dual-port FeFET with the reduction of the equivalent IL thickness can be an effective way to reduce the operating voltage of the FeFET for future embedded-memory applications.