[PS-2-17] Dual Word Line Enabled Energy-Efficient High-Speed RFET based 1T-eDRAM
High-speed and energy-efficient embedded capacitorless (1T) DRAM can be realized by enabling Schottky tunneling of holes during write-1 operation in a two-world line (2-WL) architecture of reconfigurable transistor (RFET). In contrast, the topology with single WL is more suitable for standalone applications due to a relatively longer write time (~ 17 ns) resulting from impact ionization based write-1 mechanism. Results showcase a better utilization of inherent physical phenomenon of RFET to enhance 1T-DRAM metrics (retention time of ~1.7 s at 85 °C, current ratio of ~103, with an energy consumption of ~4 fJ at read and write time of 1 ns).