The Japan Society of Applied Physics

[PS-2-22] 2 bit/cell Dynamic Flash Memory with Three Gates

Koji Sakui1, Yisuo Li1, Yoshihisa Iwata1, Masakazu Kakumu1, Nozomu Harada1 (1. Unisantis Electronics Singapore (Singapore))

https://doi.org/10.7567/SSDM.2023.PS-2-22

This paper proposes 2 bit/cell Muti-Level Cell Dynamic Flash Memory (MLC DFM) with three gates for realizing a long retention time. MLC DFM has been validated by Silvaco TCAD simulation. Four level retention time achieves 100 ms at 85 ℃.