The Japan Society of Applied Physics

14:12 〜 14:14

[SO-PS-02-22] 2 bit/cell Dynamic Flash Memory with Three Gates

Koji Sakui1, Yisuo Li1, Yoshihisa Iwata1, Masakazu Kakumu1, Nozomu Harada1 (1. Unisantis Electronics Singapore (Singapore))

This paper proposes 2 bit/cell Muti-Level Cell Dynamic Flash Memory (MLC DFM) with three gates for realizing a long retention time. MLC DFM has been validated by Silvaco TCAD simulation. Four level retention time achieves 100 ms at 85 ℃.