The Japan Society of Applied Physics

1:36 PM - 1:38 PM

[SO-PS-12-04] A sub-50-mV supply, recursive stacking body bias NAND gate for extremely low-voltage energy harvesting

Shintaro Sumi1, Hikaru Sebe1, Daisuke Kanemoto1, Tetsuya Hirose1 (1. Osaka Univ. (Japan))

This paper presents a recursive stacking body-bias NAND for extremely low voltage application. The voltage gain of the proposed NAND and the effect of the leakage current are improved and suppressed, respectively, by adding NAND gates recursively. A prototype chip was fabricated in a 180-nm CMOS process and demonstrated that the voltage swing was improved by 22% at 50 mV supply.