International Display Workshops General Incorporated Association

13:40 〜 14:00

[AMD1-3] Device Model of Positive Bias Temperature Stress Instability for Oxide Semiconductor TFTs

*Katsumi Abe1、Kazuki Ota1、Takeshi Kuwagaki1 (1.Silvaco Japan Co., Ltd. (Japan))

Positive bias temperature stress instability, Oxide semiconductor TFT, Device simulation

https://doi.org/10.36463/idw.2021.0125

We propose a device model for oxide semiconductor thin-film transistors (OS TFTs) under positive bias temperature stress (PBTS). This model is a function of the channel interface electric field, and device simulations using this model reproduce measured PBTS degradation. The model is suitable for PBTS instability evaluation of OS TFTs.