The Japan Society of Applied Physics

14:45 〜 15:00

[H-9-04] Understanding the Tunneling Behavior in 2D Based Floating Gate Type Memory Device by Measuring Floating Gate Voltage

〇Taro Sasaki1, Keiji Ueno2, Takashi Taniguchi3, Kenji Watanabe3, Tomonori Nishimura1, Kosuke Nagashio1 (1. Univ. of Tokyo(Japan), 2. Saitama Univ.(Japan), 3. NIMS(Japan))

https://doi.org/10.7567/SSDM.2020.H-9-04