2015年 第76回応用物理学会秋季学術講演会

講演情報

一般セッション(口頭講演)

13 半導体 » 13.3 絶縁膜技術

[14a-4C-1~10] 13.3 絶縁膜技術

2015年9月14日(月) 09:00 〜 11:45 4C (432)

座長:渡部 平司(阪大),井上 真雄(ルネサス)

10:00 〜 10:15

[14a-4C-5] Fabrication and MOS interface properties of ALD AlYO3/GeOx/Ge gate stacks with plasma post oxidation

〇(M2)Mengnan Ke1, Xiao Yu1, Rui Zhang1, Jian Kang1, Chih-Yu Chang1, Mitsuru Takenaka1, Shinichi Takagi1 (1.Tokyo Univ.)

キーワード:Ge

As one of the promising gate stacks, Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge structures realized by PPO [1,2] have been shown to have EOT of 1 nm or thinner, and low Dit of ~1011 eV-1cm-2. However, one of the remaining critical issues is a large amount of slow traps, attributable to any defects inside gate insulators [3-5]. It has been recently reported that Y-doped GeOx interface layers fabricated by sputtering can provide the superior MOS interface properties small hysteresis and low Dit.[6-8] In this study, thus, we study the effect of ALD AlYO3 layers, replacing Al2O3 in the PPO process, on the MOS interface properties including slow traps.