2016年 第77回応用物理学会秋季学術講演会

講演情報

一般セッション(口頭講演)

10 スピントロニクス・マグネティクス » 10.4 半導体・有機・光・量子スピントロニクス

[14p-C41-1~21] 10.4 半導体・有機・光・量子スピントロニクス

2016年9月14日(水) 13:15 〜 19:00 C41 (日航4階朱雀A)

大矢 忍(東大)、清水 大雅(農工大)

17:30 〜 17:45

[14p-C41-16] A New Computing Architecture Using Ising Spin Model for Solving Combinatorial Optimization Problems Implemented on FPGA

Takanari Saito1、Yusuke Kihara1、Masayuki Shiomura1、Jun-ichi Shirakashi1 (1.Tokyo Univ. Agr. & Tech.)

キーワード:Ising Spin Model, Combinatorial Optimization Problem, Logic Gate

It is well known that Ising spin model represents the physical properties of ferromagnetic materials in terms of statistical mechanics. Recently, the new computing architecture called Ising computing has been proposed using superconductors and CMOS circuits, to simulate the Ising spin model, in which this method maps the combinatorial optimization problems to the ground state search of the model. In this report, a new computing architecture using Ising spin model was implemented using logic gates, and the Ising computing based on logic gates was investigated to solve combinatorial optimization problems.