[21p-C105-1~11] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[21p-C105-9] Accurate Evaluation of Interface Trap Density at InAs MOS Interfaces by C-V Measurements at Low Temperatures

〇(M2)Ryohei Yoshizu¹, Kei Sumita¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1.Univ. Tokyo)

Keywords:semiconductor, InAs, MOSFET

A method of accurately evaluating the interface trap density (D_it) by using the high-frequency C-V curves at InAs MOS interfaces is experimentally examined. Low-temperature measurements are performed to suppress the response of interface states. We study the impacts of the accuracy of the oxide capacitance, the distribution function, and the C-V hysteresis due to slow traps on D_it evaluated by the high-frequency C-V (Terman) method. It is found that temperatures lower than 40 K and the C-V measurements in limited voltage ranges are indispensable in the accurate evaluation of D_it.