[K-5] Advanced Neuron and AI Systems

[K-5-02] A 1.2nJ/Classification 2.4mm² Wired-Logic Neuron Cell Array Using Logically Compressed Non-Linear Function Blocks in 0.18µm CMOS

〇Rei Sumikawa¹, Kota Shiba¹, Atsutake Kosuge¹, Mototsugu Hamada¹, Tadahiro Kuroda¹ (1. Univ. of Tokyo (Japan))

Presentation style: Online

https://doi.org/10.7567/SSDM.2022.K-5-02

A 5.3 times smaller and 2.6 times more energy-efficient wired-logic processor which infers MNIST with 90.6% accuracy and 1.2nJ of energy consumption is developed. To improve area efficiency of wired-logic architecture, non-linear neural network (NNN), which is a neuron and synapse efficient network, and a logical compression technology which downsizes the circuit area of neurons are proposed. Since all of the neuron cell array is composed of combinational circuits, low voltage operation of 0.9V (half of the rated voltage in 0.18µm) is realized.