Investigation of Low-Cost Stress Memorization Process on Layout and Low-Frequency Noise Performance for Strained-Si nMOSFETs

C. W. Kuo; S. L. Wu; H. Y. Lin; Y. T. Huang; S. J. Chang; D. G. Hong; C. Y. Wu; Y. C. Cheng; O. Cheng

doi:https://doi.org/10.7567/SSDM.2010.P-3-13

[P-3-13] Investigation of Low-Cost Stress Memorization Process on Layout and Low-Frequency Noise Performance for Strained-Si nMOSFETs

C. W. Kuo¹、S. L. Wu²、H. Y. Lin¹、Y. T. Huang¹、S. J. Chang¹、D. G. Hong²、C. Y. Wu²、Y. C. Cheng³、O. Cheng³ (1.National Cheng Kung Univ.、2.Cheng Shiu Univ.、3.UMC , Taiwan)

https://doi.org/10.7567/SSDM.2010.P-3-13

2010 International Conference on Solid State Devices and Materials

[P-3-13] Investigation of Low-Cost Stress Memorization Process on Layout and Low-Frequency Noise Performance for Strained-Si nMOSFETs