[M-7-1] Strategy of STT-MRAM Cell Design and Its Power Gating Technique for Low-Voltage and Low-Power Cache Memories T. Ohsawa1、S. Ikeda1、T. Hanyu1、H. Ohno1、T. Endoh1 (1.Tohoku Univ. (Japan)) https://doi.org/10.7567/SSDM.2013.M-7-1