[PS-5-5] Emulation of High Frequency Substrate Noise in CMOS Digital Circuits with Effects of Adjusting Clock Skew

S. Shimazaki¹, S. Taga¹, T. Makita¹, N. Azuma¹, N. Miura¹, M. Nagata¹ (1.Kobe Univ. (Japan))

https://doi.org/10.7567/SSDM.2013.PS-5-5