[J-3-5L] The Guideline of Si/SiGe Hetero-Junction Design in Parallel Plate Style TFETs (PP-TFETs) for Si CMOS Platform Implementation
M. Goto1、Y. Kondo1、Y. Morita2、S. Migita2、A. Hokazono1、H. Ota2、M. Masahara2、S. Kawanaka1
(1.Toshiba Corp.、2.GNC, AIST (Japan))
https://doi.org/10.7567/SSDM.2014.J-3-5L