[F-10] CMOS and Memory Applications of Low Dimensional Materials II

2022年9月29日(木) 16:00 〜 17:45 201 (2F)

Session Chair: Takamasa Kawanago (Tokyo Tech), Sakura Takeda (NAIST)

+全てマイスケジュールに登録

16:00 〜 16:30

[F-10-01 (Invited)] Hybrid 2D/CMOS microchips for memristive technologies

〇Mario Lanza¹ (1. KAUST (Saudi Arabia))

Presentation style: Online

16:30 〜 16:45

[F-10-02] Neural Network Hardware Accelerator using Memristive Crossbar Array based on Wafer-Scale 2D HfSe2

〇Sifan Li¹, Samarth Jain¹, Mei-Er Pam¹, Li Chen¹, Yu-Chieh Chien¹, Xuanyao Fong¹, Dongzhi Chi², Kah-Wee Ang^1,2 (1. National Univ. of Singapore (Singapore), 2. Inst. of Material Res. and Engineering (Singapore))

Presentation style: On-site (in-person)

16:45 〜 17:00

[F-10-03] Self-selective Monolayer MoS₂ Memtransistor Crossbar Array for In-memory Computing Applications

〇Xuewei Feng¹, Kah-Wee Ang² (1. Shanghai Jiao Tong Univ. (China), 2. National Univ. of Singapore (Singapore))

Presentation style: Online

17:00 〜 17:15

[F-10-04] Demonstration of Single-gate MoS2 Tunnel FET with Natural In-plane Heterojunction

〇Tomohiro Fukui¹, Tomonori Nishimura¹, Takashi Taniguchi², Kenji Watanabe², Kosuke Nagashio¹ (1. Univ. of Tokyo (Japan), 2. Inst. for Materials Science (Japan))

Presentation style: On-site (in-person)

17:15 〜 17:45

[F-10-05 (Invited)] 2D transistor top and bottom gate stack scaling in 300mm pilot line

〇Quentin Smets¹, Tom Schram¹, Daire Cott¹, Anish Dangol¹, Dennis Lin¹, Souvik Ghosh¹, Rudy Verheyen¹, Steven Brems¹, Benjamin Groven¹, Pierre Morin¹, Inge Asselberghs¹, Gouri Sankar Kar¹ (1. imec (Belgium))

Presentation style: Online

セッション情報

[F-10] CMOS and Memory Applications of Low Dimensional Materials II

[F-10-01 (Invited)] Hybrid 2D/CMOS microchips for memristive technologies

[F-10-02] Neural Network Hardware Accelerator using Memristive Crossbar Array based on Wafer-Scale 2D HfSe2

[F-10-03] Self-selective Monolayer MoS₂ Memtransistor Crossbar Array for In-memory Computing Applications

[F-10-04] Demonstration of Single-gate MoS2 Tunnel FET with Natural In-plane Heterojunction

[F-10-05 (Invited)] 2D transistor top and bottom gate stack scaling in 300mm pilot line

認証

セッション情報

[F-10] CMOS and Memory Applications of Low Dimensional Materials II

[F-10-01 (Invited)] Hybrid 2D/CMOS microchips for memristive technologies

[F-10-02] Neural Network Hardware Accelerator using Memristive Crossbar Array based on Wafer-Scale 2D HfSe2

[F-10-03] Self-selective Monolayer MoS2 Memtransistor Crossbar Array for In-memory Computing Applications

[F-10-04] Demonstration of Single-gate MoS2 Tunnel FET with Natural In-plane Heterojunction

[F-10-05 (Invited)] 2D transistor top and bottom gate stack scaling in 300mm pilot line

認証

[F-10-03] Self-selective Monolayer MoS₂ Memtransistor Crossbar Array for In-memory Computing Applications