The Japan Society of Applied Physics

[J-7-1] Ultra Low-Frequency Noise in Vertical MOSFETs Having Tunable Threshold Voltage Fabricated with 60 nm CMOS Technology on 300 mm Wafer Process

T. Imamoto1,2、T. Endoh1,2,3 (1.Graduate School of Engineering, Tohoku Univ.、2.ACCEL, JST、3.Center for Innovative Integrated Electronic Systems, Tohoku Univ. (Japan))

https://doi.org/10.7567/SSDM.2014.J-7-1