The 26th International Display Workshops (IDW '19)

Presentation information

Oral Presentation

[AMD4] Emerging TFTs

Thu. Nov 28, 2019 9:00 AM - 10:20 AM Mid-sized Hall B (1F)

Chair: Hyun Jae Kim (Yonsei Univ.)
Co-Chair: Yosei Shibata (Tohoku Univ.)

9:50 AM - 10:05 AM

[AMD4-4L] Integrated Polycrystalline Silicon Photomask Technology for Low-Temperature Polycrystalline Silicon (LTPS) TFTs

*Jia-Hong Ye1, Ching-Liang Huang1, Kuo-Yu Huang1, Maw-Song Chen1, Wen-Ching Tsai1, Wei-Ming Huang1, Yang-An Wu1 (1. AUO (Taiwan))

Keywords:LTPS TFTs, Hybrid Backplane, LTPO

A novel Four-Photomask complementary metal oxide semiconductor (CMOS) technology for low temperature polycrystalline silicon (poly-Si) thin film transistors (LTPS TFTs) was proposed in the first time. The combination of poly-Si layer and P plus (P+) region definitions within one lithography process was realized by a half-tone photomask. In this paper, the characteristics of TFTs within a half-tone Poly-Si Photomask of lithography processes were reported and compared with electrical characteristics of typical Six-Photomask lithography processes. The Integrated Poly-Si Photomask Technology can be applied to reduce the numbers of photomask of making an IGZO and LTPS Hybrid TFTs Array.