The 26th International Display Workshops (IDW '19)

講演情報

Poster Presentation

[AMDp2] Active-Matrix Devices

2019年11月28日(木) 14:30 〜 17:00 Main Hall (1F)

14:30 〜 17:00

[AMDp2-11] Analysis of Horizontal-Mura Caused by Reset’s Abnormal Delay of GOA Output

*Xinmao Qiu1, Yao Liu1, Hongjiang Wu1, Hongtao Lin1, Baoqiang Wang1, Wenchao Wang1, Yaochao Lv1, Guichun Hong1, Min Zhou1, Zuwen Liu1 (1. Fuzhou BOE Optoelectronics Technology Co., Ltd (China))

キーワード:Gate Driver on Array, Horizontal-Mura, Leakage Current, Array Design

A rare failure named Horizontal-Mura Caused by Reset’s abnormal Delay of GOA Output is studied systemically. By increasing frame frequency, changing TFT size ratio and increasing channel Length, the leakage current of voltage Gout’s Gate (PU) can be reduced, and Mura phenomenon can be significantly alleviated.