[AMDp2] Active-Matrix Devices

[AMDp2-13] A Narrow Border Design and Low Power Consumption of a-Si:H TFT Gate Driver Circuit

Jhongciao Ke^1,2, Techen Chung², Chiate Liao², Chiamin Yu², Yanbing Qiao², Zhongfei Zou², *Limei Jiang², Xiaojun Guo¹ (1. Shanghai Jiao Tong University (China), 2. InfoVision Optoelectronics (Kunshan) Co., Ltd. (China))

キーワード：Gate driver on array, GOA, Narrow border, Low power consumption

In this paper, an integrated hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver circuit design for narrow border and low power consumption in the small-size panel is proposed. The border can be decreased from 1 mm to 0.8 mm, which can be further improved to 0.65 mm. In addition, the power consumption of circuit can be reduced by using the 25% duty ratio 8 clock signals with high reliability.