[20a-B4-1~11] 13.5 Si process technology

Fri. Sep 20, 2013 9:00 AM - 12:00 PM B4 (TC2 1F-106)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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9:00 AM - 9:15 AM

[20a-B4-1] Scallop reduction processing of Si trench sidewalls by ICP-RIE using F₂+He gas

^○Ryo Mikasa¹, Satoko Shinkai², Yuki Noda³, Shinichi Motoyama³ (Kyushu Inst. of Tech.¹, CMS, Kyushu Inst. of Tech.², SAMCO Inc.³)

9:15 AM - 9:30 AM

[20a-B4-2] Technique of Wide Area Si Etching with ClF₃ Cluster Beam

^○Yu Yoshino¹, Takehiko Senoo¹, Kunihiko Koike¹, Toshio Seki², Takaaki Aoki², Jiro Matsuo² (Iwatani Corp.¹, Kyoto Univ.²)

9:30 AM - 9:45 AM

[20a-B4-3] Minimal System of Micro-Plasma Dry Etcher Equipment

^○Hiroyuki Tanaka², Shizuka Nakano^1,2, Yoshiki Shimizu^1,2, Hisato Ogiso^1,2, Shinji Futagawa³, Hideaki Yoshioka³, Takahiro Fukuda³, Yoshinori Uchiyama³, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (AIST¹, MINIMAL², Design Network³)

9:45 AM - 10:00 AM

[20a-B4-4] Influence of edge beveling in small diameter wafer for resist coating

^○Shuuji Okuda¹, Norio Umeyama^1,2, Atsushi Yamazaki^1,3, Haruo Sumizawa^1,3, Koichiro Ichikawa^1,3, Sho Takeuchi^1,4, Yoshihisa Sensu^1,4, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST², Fujikoshi³, LTJ⁴)

10:00 AM - 10:15 AM

[20a-B4-5] Half-Inch Silicon CVD Reactor Using Concentrated Infrared Light Heater

^○Ning Li¹, Hitoshi Habuka¹, Shin-ichi Ikeda^2,3, Yuki Ishida^2,3, Shiro Hara^2,3 (Yokohama Nat. Univ.¹, AIST², Minimal Fab Development Association³)

10:15 AM - 10:30 AM

[20a-B4-6] Sputter Deposition Equipment for Minimal Fab

^○Hisato Ogiso^1,2, Shizuka Nakano^1,2, Ken Yukimura¹, Akihiko Kato^2,3, Yuki Yabuta^2,3, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (AIST¹, Minimal², Seinan³)

Break (10:30 AM - 10:45 AM)

10:45 AM - 11:00 AM

[20a-B4-7] Mechanism of Thermal Oxidation Process using the Minimal Laser Heating Equipment

^○Haruki Toonoe², Takashi Yajima², Takashi Chiba^1,2, Masao Terada^1,2, Shinichi Ikeda^2,3, Sommawan Khumpuang^2,3, Shiro Hara^2,3 (Sakaguchi E.H VOC Corp¹, Minimal², AIST³)

11:00 AM - 11:15 AM

[20a-B4-8] Control of the Uniformity of Lithography Resolution in Minimal Mask-less Exposure System.

^○Yuuji Kitayama¹, Haruki Toonoe¹, Yoshie Ishii^1,2, Ryouichi Irita^1,2, Kenji Miyake^1,2, Sommawan Khumpuang^1,3, Shiro Hara^1,3 (MINIMAL¹, PMT², AIST³)

11:15 AM - 11:30 AM

[20a-B4-9] CMP processes for Si and SiO₂ surfaces using a minimal CMP machine

^○Norio Umeyama^1,2, Fumito Imura^1,2, Katsuhiko Nakato¹, Kazutaka Shibuya^1,3, Yoshio Nakamura^1,3, Kouichiro Ichikawa³, Sommawan Khumpuang^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST², Fujikoshi Machinery³)

11:30 AM - 11:45 AM

[20a-B4-10] Cleanroom-Free Minimal Air Circulation System For PLAD

^○Takashi Yajima¹, Sommawan Khumpuang^1,2, Hitoshi Maekawa^1,2, Shiro Hara^1,2 (MINIMAL¹, AIST²)

11:45 AM - 12:00 PM

[20a-B4-11] Quick Thermal Oxidation Process using Minimal Resistance Furnace

^○Shinnosuke Suzuki^1,2, Ayami Yaginuma^1,2, Kiyohiko Morikawa^1,2, Masashi Hattori^1,2, katsuhiko Nakato², Takanori Mikahara², Ikeda Shinichi^2,3, Sommawan Khumpuang^2,3, Shiro Hara^2,3 (KOYO Thermo Systems¹, MINIMAL², AIST³)

Session information

[20a-B4-1~11] 13.5 Si process technology