9:00 AM - 9:15 AM

[20a-C8-1] Contact Hole Fabrication Using Directed Self-Assembly Lithography

^○Ayako Kawanishi¹, Yuriko Seino¹, Masahiro Kanno¹, Hirokazu Kato¹, Hironobu Sato¹, Katsutoshi Kobayashi¹, Hiroki Yonemitsu¹, Mitsuhiro Omura¹, Yusuke Kasahara¹, Tsubasa Imamura¹, Noriko Sakurai¹, Tsukasa Azuma¹ (Toshiba corporation¹)

9:15 AM - 9:30 AM

[20a-C8-2] Investigation of Scaling Law for Cosmic-ray Neutron Induced Multiple Cell Upsets

Kenshiro Sakuta¹, ^○Shin-ichiro Abe^1,2, Yukinobu Watanabe¹, Ryo Harada³, Masanori Hashimoto³, Hiroshi Fuketa⁴, Taiki Uemura⁵ (Kyushu Univ.¹, JSPS Research Fellow², Osaka Univ.³, IIS, Univ. of Tokyo⁴, Fujitsu Semiconductor Ltd.⁵)

9:30 AM - 9:45 AM

△ [20a-C8-3] Investigation of Mechanical-Stress Reduction in 3D IC with Room Temperature Curing Adhesive

^○Hisashi Kino¹, Takafumi Fukusima², Mitsumasa Koyanagi², Tetsu Tanaka^1,3 (Tohoku Univ.¹, Tohoku Univ.², Tohoku Univ.³)

9:45 AM - 10:00 AM

[20a-C8-4] Novel Optoelectronic Power Amplifier Composed of Si Solar Cell and LED

^○Kensho Okamoto¹, Junichi Fujita¹, Tetsuo Hattori¹ (Kagawa Univ.¹)

10:00 AM - 10:15 AM

[20a-C8-5] Humidity Testing of Eternal Memory “Digital Rosetta Stone”

^○Taketoshi Matsumoto¹, Tomoki Akai¹, Shigeki Imai¹, Hikaru Kobayashi¹ (ISIR, Osaka Univ., CREST-JST¹)

10:15 AM - 10:30 AM

[20a-C8-6] Floating Gate Memory with Three-Dimensional Nanodot Array Formed by Bio-Layer-by-Layer Method

^○Hiroki Kamitake^1,2, Mutsunori Uenuma², Yasuaki Ishikawa^1,2, Ichiro Yamashita^1,2, Yukiharu Uraoka^1,2 (NAIST¹, CREST²)

Break (10:30 AM - 10:45 AM)

10:45 AM - 11:00 AM

[20a-C8-7] Gate structure dependence of electrical characteristics in floating-gate type poly-Si channel FinFET flash memories

^○Yongxun Liu¹, Takashi Matsukawa¹, Kazuhiko Endo¹, Shinichi Ouchi¹, Junichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Wataru Mizubayashi¹, Yukinori Morita¹, Shinji Migita¹, Hiroyuki Ota¹, Meishoku Masahara¹ (AIST¹)

11:00 AM - 11:15 AM

[20a-C8-8] Comparative study of electrical characteristics for TiN metal and poly-Si gated charge trapping type FinFET flash memories

^○Yongxun Liu¹, Takashi Matsukawa¹, Kazuhiko Endo¹, Shinichi Ouchi¹, Junichi Tsukada¹, Hiromi Yamauchi¹, Yuki Ishikawa¹, Wataru Mizubayashi¹, Yukinori Morita¹, Shinji Migita¹, Hiroyuki Ota¹, Meishoku Masahara¹ (AIST¹)

11:15 AM - 11:30 AM

▲ [20a-C8-9] Analysis of Photoresponse in SOI FinFET

^○(D)Dedy Putranto^1,3, Kazuhiko Endo², Meishoku Masahara², Hiroaki Satoh¹, Atsushi Ono¹, Purnomo Priambodo³, Djoko Hartanto³, Hiroshi Inokawa¹ (Res. Inst. of Electron., Shizuoka Univ.¹, Nanoelectron. Res. Inst., Nat. Inst. of Adv. Ind. Sci. & Technol.², Electrical Eng. Dept., Univ. of Indonesia³)

11:30 AM - 11:45 AM

[20a-C8-10] Methodology for Evaluating Operation Temperature of FinFETs in a Circuit

^○(P)Tsunaki Takahashi¹, Shunri Oda², Ken Uchida¹ (Keio Univ.¹, Tokyo Inst. Tech.²)

11:45 AM - 12:00 PM

[20a-C8-11] Mechanism of Recovery from Negative Bias Temperature Instability

^○Yoshiki Yonamoto¹ (Hitachi, Ltd., Yokohama Laboratory¹)

12:00 PM - 12:15 PM

[20a-C8-12] Estimation of Effective Channel Length from MOSFET C-V Curve Measured by Charge-Based Capacitance Measurement

^○Katsuhiro Tsuji¹, Kazuo Terada¹ (Hiroshima City Univ.¹)

Session information

[20a-C8-1~12] 13.6 Silicon devices / Integration technology